`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/30 09:23:03
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top
( 
  //sim_clk
  input             adc_ref_clk     ,
  input             Tri_pluse_start ,
  input             Tri_pluse_stop  ,
  //ddr4-物理接口
  input             sys_rstn        ,//复位按键
  input             c0_sys_clk_n    ,
  input             c0_sys_clk_p    ,
  output            c0_ddr4_act_n   ,
  output    [16:0]  c0_ddr4_adr     ,
  output    [1:0]   c0_ddr4_ba      ,
  output    [0:0]   c0_ddr4_bg      ,
  output    [0:0]   c0_ddr4_ck_c    ,
  output    [0:0]   c0_ddr4_ck_t    ,
  output    [0:0]   c0_ddr4_cke     ,
  output    [0:0]   c0_ddr4_cs_n    ,
  inout     [7:0]   c0_ddr4_dm_n    ,
  inout     [63:0]  c0_ddr4_dq      ,
  inout     [7:0]   c0_ddr4_dqs_c   ,
  inout     [7:0]   c0_ddr4_dqs_t   ,
  output    [0:0]   c0_ddr4_odt     ,
  output            c0_ddr4_reset_n 
);

//wire define 
wire        ui_clk              ;
wire        peripheral_aresetn  ;

wire        adc_data_clk        ;
wire        adc_data_rstn       ;
wire [15:0] adc_sim_data        ;
wire        adc_sim_data_vaild  ;

wire        ud_wclk             ;
wire [63:0] ud_wdata            ;
wire        ud_wde              ;
wire        ud_wfifo_rst        ;
wire        ud_wvs              ;
wire        ud_wvs_clk          ;
wire        ud_wfull            ;
wire [7:0]  wbuf_sync_o         ;
wire        fdma_wirq           ;

wire        Tti_wirq            ;

clk_wiz_0 clk_wiz_0
(
    .clk_out1           ( adc_data_clk       ),
    .locked             ( adc_data_rstn      ),
    .clk_in1            ( adc_ref_clk        )
);


data_sim #(
    .DATA_WIDTH ( 16 ))
 u_data_sim (
    .data_clk           ( adc_data_clk        ),
    .data_rstn          ( adc_data_rstn       ),

    .data_out           ( adc_sim_data        ),
    .data_vaild         ( adc_sim_data_vaild  ) 
);


dbuf_ctrl #(
    .DATA_WIDTH ( 64 ))
 u_dbuf_ctrl (
    .adc_data_clk       ( adc_data_clk        ),
    .adc_data_rstn      ( adc_data_rstn       ),
    .adc_data_all       ( {adc_sim_data,
                          adc_sim_data,
                          adc_sim_data,
                          adc_sim_data}       ),
    .adc_wvs_clk        ( adc_data_clk        ),
    .Tri_pluse_start    ( Tri_pluse_start     ),
    .Tri_pluse_stop     ( Tri_pluse_stop      ),
    //.Tri_pluse_clk      ( adc_data_clk        ),
    .Tri_pluse_clk      ( adc_ref_clk         ),

    .ud_wclk            ( ud_wclk             ),
    .ud_wdata           ( ud_wdata            ),
    .ud_wde             ( ud_wde              ),
    .ud_wfifo_rst       ( ud_wfifo_rst        ),
    .ud_wvs             ( ud_wvs              ),
    .ud_wvs_clk         ( ud_wvs_clk          ),
    .ud_wfull           ( ud_wfull            ),
    .fdma_wirq          ( fdma_wirq           )
);

Tri2pc_gen #(
    .LAST_TIME ( 32'd10 ))
 u_Tri2pc_gen (
    .clk                ( ui_clk              ),
    .rstn               ( peripheral_aresetn  ),
    .fdma_wirq          ( fdma_wirq           ),
    .wbuf_sync          ( wbuf_sync_o         ),

    .Tti_wirq           ( Tti_wirq            ) 
);


system_wrapper system_wrapper_i
(
    .c0_ddr4_act_n      (c0_ddr4_act_n        ),
    .c0_ddr4_adr        (c0_ddr4_adr          ),
    .c0_ddr4_ba         (c0_ddr4_ba           ),
    .c0_ddr4_bg         (c0_ddr4_bg           ),
    .c0_ddr4_ck_c       (c0_ddr4_ck_c         ), 
    .c0_ddr4_ck_t       (c0_ddr4_ck_t         ),
    .c0_ddr4_cke        (c0_ddr4_cke          ),
    .c0_ddr4_cs_n       (c0_ddr4_cs_n         ),
    .c0_ddr4_dm_n       (c0_ddr4_dm_n         ),
    .c0_ddr4_dq         (c0_ddr4_dq           ),
    .c0_ddr4_dqs_c      (c0_ddr4_dqs_c        ),
    .c0_ddr4_dqs_t      (c0_ddr4_dqs_t        ),
    .c0_ddr4_odt        (c0_ddr4_odt          ),
    .c0_ddr4_reset_n    (c0_ddr4_reset_n      ),
    .c0_sys_clk_n       (c0_sys_clk_n         ),
    .c0_sys_clk_p       (c0_sys_clk_p         ),
    .sys_rst            (~sys_rstn            ),
    .init_calib_complete(init_calib_complete  ),

    .ui_clk             (ui_clk               ),
    .peripheral_aresetn (peripheral_aresetn   ),

    .ud_wclk            (ud_wclk              ),
    .ud_wdata           (ud_wdata             ),
    .ud_wde             (ud_wde               ),
    .ud_wfifo_rst       (ud_wfifo_rst         ),
    .ud_wvs             (ud_wvs               ),
    .ud_wvs_clk         (ud_wvs_clk           ),
    .ud_wfull           (ud_wfull             ),
    .wbuf_sync_o        (wbuf_sync_o          ),//clk domain : ui_clk
    .fdma_wirq          (fdma_wirq            ) //clk domain : ui_clk
);

// vio_0 vio_0 (
//    .clk                 (adc_data_clk         ), 
//    .probe_out0          (Tri_pluse_start      ),
//    .probe_out1          (Tri_pluse_stop       )
// );

endmodule
